With the rapid growth of the Internet in recent years, a large scale broadband connection in a subscriber access network has been required. The mainstream of a system containing the broadband access network is a passive optical networks (PON) system in which a parent station device (optical line terminal (OLT)) is connected to subscriber devices (optical network units (ONUs)) through an optical fiber. The system structure is internationally standardized in, for example, Non-Patent Document 1.
In the PON system, a time division multiplexing (TDM) method of performing temporal multiplexing is applied as a method of receiving light signals from the respective subscriber devices (ONUs). Therefore, a common system capable of containing the plurality of subscriber devices (ONUs) can be constructed using a single-core optical fiber transmission line, and hence the broadband access network can be economically constructed.
The temporally multiplexed signals are burst light signals obtained by intermittently emitting/interrupting the light signals, and hence technical problems specific to input burst light signals occur in the parent station device (OLT) which is a receiver device.
A normal optical receiver provided in the parent station device (OLT) includes an optical preamplifier for converting an input burst light signal into an electrical signal (input data) having a discriminable amplitude, and a data reproducing (clock and data recovery (CDR)) circuit for extracting a clock component from the input data and performing data recovery based on phase synchronization information. A phased lock loop (PLL) circuit using a continuous voltage controlled oscillator is normally used as a clock extraction system in the data recovery circuit. In the PLL system, a control signal substantially close to a DC component is applied as a control signal for frequency and phase control. This is used to suppress fluctuation components (jitters) generated from the oscillator and the PLL. Accordingly, it is essentially difficult for a feedback-controlled clock extraction circuit such as the PLL to obtain high-speed response characteristics.
On the other hand, the burst light signals in the PON system described above include light signals output from the plurality of subscriber devices (ONUs) with different transmission distances, and hence the respective burst light signals have various different reception phases. In addition, the frequencies of the burst light signals are synchronized with frequencies output from the respective subscriber devices (ONUs), and thus have a relative frequency deviation. Therefore, the data recovery circuit in the parent station device (OLT) is required to have a function for performing clock extraction and data recovery based on phase synchronization for each of the burst light signals at high speed. However, as described above, in the normal PLL system, it is difficult to realize stable clock extraction from a light signal whose frequency and phase vary at high speed.
A data recovery circuit for extracting a clock from the burst light signal at high speed has been proposed (see, for example, Patent Document 1). The conventional data recovery circuit generates, from received data, a gating signal synchronized with a rising phase or falling phase of input data. In an embodiment described in Patent Document 1, a toggle flip-flop whose output logic is reversed at a rising or falling edge of the input data is applied as a gating signal generating means. A gated oscillator which performs oscillation outputting or stopping in instant synchronization with the gating signal is provided, and hence the clock synchronized with the rising phase or falling phase of the input data is generated. In the embodiment, outputs of two gated oscillators which perform oscillation outputting or stopping based on the positive logic and negative logic of the gating signal are combined in an OR gate, and hence clocks instantly synchronized in phase with the input data can be successively generated.
The conventional data recovery circuit provides a high-speed clock extraction means even when phase information included in data input from the respective subscriber devices (ONUs) are uneven and temporally intermittent burst light signals are input.
Patent Document 1: JP 2005-45525 A
Non-Patent Document 1: IEEE 802.3ah Standard (2004)